This invention relates to a silicon-on-insulator (SOI) device, and more particularly to a SOI transistor having a double gate structure.
As demand on electronic appliance such as portable wireless electronic system is increased recently, the semiconductor device with high integration, high performance, low voltage and low power is interested and developed.
A method for lowering a threshold voltage of a MOSFET is typically used in accomplishing the lower driving voltage. However, the leakage current is increased due to the lowering threshold voltage of a MOSFET so that the electric characteristic of device is degraded. Various method for lowering a threshold voltage are proposed. Among various method, the semiconductor integration technology using a silicon on insulator (SOI) wafer where an oxide layer is sandwiched between two silicon layers is interested. The semiconductor device embodied in the SOI wafer has advantages of high performance due to low junction capacitance, low driving voltage due to low threshold voltage and removal of latch-up due to complete device isolation, as compared with the semiconductor device embodied in a silicon bulk wafer.
FIG.1 is a sectional view of a SOI transistor embodied in a SOI wafer in the prior art. A SOI wafer 10 including a supporting substrate 11, a buried oxide layer 12 and a silicon layer 13 is prepared and an isolation layer 14 is formed in the silicon layer 13 to be contacted with the buried oxide layer 12. With a conventional process, a gate oxide 15 and a gate 16 are formed over the silicon layer 13 and source and drain regions 17 are formed in the silicon layer 13 at the both sides of the gates 16.
In the above SOI transistor, the source and drain regions 17 are formed to be contacted with the buried oxide layer 12 and the depletion region is removed to reduce the junction capacitance, thereby accomplishing the high performance. Besides, the complete device isolation is accomplished by the buried oxide layer 12 and the isolation layer 14 to prevent the latch-up.
However, the SOI transistor can accomplish the high performance due to the lower threshold voltage as compared with the conventional transistor, but there is a limit to lower the threshold voltage of the SOI transistor.
Recently, a study on a SOI device having a double gate has been progressed, which is fabricated in a SOI wafer and forms two gate in stack. The SOI device having a double gate can further lower the threshold voltage by controlling the voltages applied to two gates.
When the SOI device having a double gate is fabricated, the alignment between two gates becomes an essential factor. Following the lower gate formation, because an upper gate and a source and drain regions are formed in the lower gate, the misalignment between the lower and upper gates is occurred and it increases the capacitance due to the gate overlap, thereby causing the desired phenomenon such as a gate delay.